1. Field of the Invention
The present invention relates to a method and related apparatus for internal data accessing of a computer system; more particularly, to a method and related apparatus for assigning data accessing requests to various data access paths according to their snooping and non-snooping attributions.
2. Description of the Prior Art
A computer system is an important and basic hardware appliance in our modern information society. Improving the efficiency of today's computer system is a priority for manufacturer's research and development endeavors. In general, a computer system includes a central processing unit (CPU), a system memory, a chipset and various types of peripheral devices and circuits. The CPU is designed for and capable of controlling all operations of the computer system by performing operations, processing data and executing program's instructions. The system memory provides system memory space for data storing and information involved in the operation of the CPU and the whole computer. A large number of peripherals are available for the computer system, including but not limited to: display cards for processing image display prior to output; a network card for processing network connections and other storage devices. The chipset is capable of managing data transmission and exchanges allowing the peripheral, the system memory and the CPU to interact. Since the chipset manages and services all of the data accessing requests of each peripheral, each peripheral accesses the system memory space by asking an access request to the chipset. During accessing the request, the peripheral indicates a specific desired address of the system memory space to access the required data. The chipset will then arrange these addresses into an address queue, which stores addresses requested by various peripherals. In response to the data accessing request, the requested data (e.g., data accessed from the system memory space) will be temporarily stored in a buffer of the chipset for later transmitted to the appropriate peripheral accordingly.
The efficiency of the chipset can be improved during the steps of managing the peripheral accessing data. The modern chipset has a mechanism of multiple virtual channels (VCs). For the VCs mechanism, only a physical channel is required to support multiple VCs. The chipset is capable of receiving and processing various data accessing request respectively through these VCs. This is equivalent to receiving and processing shared independent (non-interference) accessing requests through different virtual channels. For example, the standards defined in the peripheral components interconnection express (PCI-E) specification include the basic structure having multiple VCs set-up. However, to support the mechanism of multiple VCs, it is necessary to include and set-up additional circuits on the chipset. For example, there is a need for the chipset to set-up independent buffers for the multiple VCs to buffer the data and information on the different VCs respectively. Similarly, to fully utilize the mechanism of multiple VCs, the peripheral itself must support multiple VCs to perform data accessing.
In the development of the conventional peripheral, which mostly devices and circuits can only support a single VC. This is inefficient because the chipset is capable of supporting multiple VCs while the peripheral is operated under a single VC environment. Since the peripheral is still unable to realize the high efficient data accessing through multiple VCs, the additional chipset hardware that supports multiple VCs is idle.
A conventional method of a chipset with multiple VCs serves peripherals with a single VC. The method combines buffers of each different multiple VCs in serial to a larger buffer. As the peripheral receives a response of the accessing request, the response data and information can be temporarily stored into one of the buffer of a VC. If the storage space of the buffer is full, then another buffer of a next VC will be used to continuously store the response data and information, and so forth.
The above-mentioned method has disadvantages of improving the performances, because the above mentioned method can only increase the additional buffer of the chipset. For example, when the space of the address queue is limited, as the mention above, if the chipset processes an accessing request of the peripherals, the requests will firstly be arranged into the address queue. Then the accessing request is performed sequentially according to the addresses in the address queue. The response is then buffered in the buffer and transmitted back to the peripheral. If space utilized to keep the address queue is limited, the chipset can serve only a limited amount of access requests even though each buffer of the different multiple VCs is combined in serial into a larger buffer space for buffering the responses of accessing requests. Again, the efficiency of the chipset is not improved.